In a manufacturing process for a semiconductor device having, for example, a multilayer wiring structure, a resist coating process of forming a resist film by coating a resist liquid on a semiconductor wafer (hereinafter, referred to as “wafer”), an exposure process of exposing the resist film to have a preset pattern, a developing process of developing the exposed resist film, and so forth are performed in sequence. Through these processes, a resist pattern is formed on the wafer. Then, an etching process is performed on the wafer by using the resist pattern as a mask. Then, a removing process of removing the resist film or the like is performed, so that the preset pattern is formed on the wafer. By repeating these processes of forming a pattern on each of stacked layers multiple times, a semiconductor device having a multilayer wiring structure is manufactured.
When patterns are formed on the wafer repeatedly, however, a surface to be coated with the resist film needs to be planarized in order to form the resist film of the (n+1)th layer to an appropriate height after a pattern is formed on the nth layer.
Conventionally, to this end, after a processing target film is formed on the pattern of the wafer, a surface of the processing target film is planarized. The processing target film may be formed by using a method involving the processes of: coating a source material on the wafer; forming the processing target film by heating the coated source material; and removing a surface of the processing target film by etching back the processing target film through the use of, for example, a dry etching method (reactive ion etching method), as described in Patent Document 1, for example. Hereinafter, the processing target film coated and formed for the planarization of the substrate will be referred to as a SOC (Spin On Cap) film.
Patent Document 1: Japanese Patent Laid-open Publication No. 2003-218116 (paragraphs [0002] and [0003])
When using the method described in the aforementioned Patent Document 1, the coating and the heating of the source material are performed in a normal pressure atmosphere, whereas the etch-back of the SOC film is performed in a vacuum atmosphere. Thus, the process under the normal pressure atmosphere and the process under the vacuum atmosphere are required to be performed in individual systems, and the wafer needs to be transferred between these different systems. As a result, manufacturing costs for the systems would be increased and a wafer processing throughput would be reduced.
Furthermore, when performing the etch-back of the SOC film through the dry-etching method, the wafer or a film on the wafer may be damaged by plasma. Furthermore, the film on the wafer may be modified by the plasma.